The subject matter of the present application relates to microelectronic structures, e.g., structures incorporating active circuit elements, such as, without limitation, structures including at least one semiconductor chip or portion of at least one semiconductor chip, as well as assemblies incorporating microelectronic structures.
Semiconductor chips are commonly provided as individual, prepackaged units. A standard chip has a flat, rectangular body with a large front face having contacts connected to the internal circuitry of the chip. Each individual chip typically is contained in a package having external terminals connected to the contacts of the chip. In turn, the terminals, i.e., the external connection points of the package, are configured to electrically connect to a circuit panel, such as a printed circuit board. In many conventional designs, the chip package occupies an area of the circuit panel considerably larger than the area of the chip itself. As used in this disclosure with reference to a flat chip having a front face, the “area of the chip” should be understood as referring to the area of the front face.
Size is a significant consideration in any physical arrangement of chips. The demand for more compact physical arrangements of chips has become even more intense with the rapid progress of portable electronic devices. Merely by way of example, devices commonly referred to as “smart phones” integrate the functions of a cellular telephone with powerful data processors, memory and ancillary devices such as global positioning system receivers, electronic cameras, and local area network connections along with high-resolution displays and associated image processing chips. Such devices can provide capabilities such as full internet connectivity, entertainment including full-resolution video, navigation, electronic banking and more, all in a pocket-size device. Complex portable devices require packing numerous chips into a small space. Moreover, some of the chips have many input and output connections, commonly referred to as “I/Os.” These I/Os must be interconnected with the I/Os of other chips. The components which form the interconnections should not greatly increase the size of the assembly. Similar needs arise in other applications as, for example, in data servers such as those used in internet search engines where increased performance and size reduction are needed.
Microelectronic elements such as semiconductor chips which contain memory storage arrays, particularly dynamic random access memory chips (DRAMs) and flash memory chips, are commonly packaged in single- or multiple-chip packages and assemblies. Each package has many electrical connections for carrying signals, power and ground between terminals and the microelectronic elements, e.g., chips therein. The electrical connections can include different kinds of conductors such as horizontal conductors, e.g., traces, beam leads, etc., which extend in a horizontal direction relative to a contact-bearing surface of a chip, vertical conductors such as vias, which extend in a vertical direction relative to the surface of the chip, and wire bonds which extend in both horizontal and vertical directions relative to the surface of the chip.
Conventional microelectronic packages can incorporate a microelectronic element having active elements defining a memory storage array. Thus, in some conventional microelectronic elements, transistors or other active elements, constitute a memory storage array with or without additional elements. In some cases, the microelectronic element can be configured to predominantly provide memory storage array function, i.e., in which case microelectronic element may embody a greater number of active elements to provide memory storage array function than any other function. In some cases, a microelectronic element may be or include a DRAM chip, or may be or include a stacked electrically interconnected assembly of such semiconductor chips. Typically, all of the terminals of such package are placed in sets of columns adjacent to one or more peripheral edges of a package substrate to which the microelectronic element is mounted. For example, in one conventional microelectronic package 12 seen in FIG. 1, three columns 14 of terminals can be disposed adjacent a first peripheral edge 16 of the package substrate 20 and three other columns 18 of terminals can be disposed adjacent a second peripheral edge 22 of the package substrate 20. A central region 24 of the package substrate 20 in the conventional package does not have any columns of terminals. FIG. 1 further shows a semiconductor chip 11 within the package having element contacts 26 on a face 28 thereof which are electrically interconnected with the columns 14, 18 of terminals of the package 12 through wire bonds 30 extending through an aperture, e.g., bond window, in the central region 24 of package substrate 20. In some cases, an adhesive layer 32 may be disposed between the face 28 of the microelectronic element 11 and the substrate 20 to reinforce the mechanical connection between the microelectronic element and the substrate, with the wire bonds extending through an opening in the adhesive layer 32.
In light of the foregoing, certain improvements in the positioning of terminals on microelectronic packages can be made in order to improve electrical performance, particularly in assemblies which include such packages and a circuit panel to which such packages can be mounted and electrically interconnected with one another.